Many popular consumer electronics applications such as cameras and mobile handsets as well as professional electronic applications such as video surveillance and monitoring employ complementary metal-oxide-semiconductor (CMOS) image sensors (CIS). Various applications pose different requirements on the spatial and temporal resolution. In general, as sensor resolution increases, the operation of the sensors in desired frame rates involves higher data conversion rates. CMOS image sensors typically comprise a pixel matrix and a readout circuit. The pixel matrix includes a plurality of CMOS pixel sensors organized in rows and columns of a matrix. In a CMOS pixel sensor, an input light brightness is converted to a corresponding analog electrical signal by, for instance, a pinned photodiode. The readout circuitry scans the pixel matrix and outputs a digital image signal that contains the scene information. Typically, the pixels are read by selecting each row of pixels successively. At the same time, the pixel signals are read from multiple columns of the selected row.
Traditionally, the readout circuitry has included of a Correlated Double Sampling (CDS) amplifier for computing the pixel signal and for amplifying it to the required level, and an output buffer for bringing the analog signal out of the sensor, where it is conditioned and digitized. The correlated double sampling removes noise by subtracting a noisy signal value (NS) and a dark level value (N) from the same pixel. The resulting signal value (S) serves then usually as a basis for the analog-digital conversion. Most of the recent implementations include the analog-to-digital conversion (ADC) on the chip. Accordingly, the CDS amplifier is often followed by an ADC block.
The reading out of the multiple columns may be parallelized, which is advantageous especially for the high-speed applications. On the other hand, parallelism requires more circuit components. For instance, in order to read out the pixels from all columns in parallel, for each column a Correlated Double Sampling (CDS), amplification and/or AD conversion circuit is to be provided. The level of parallelization may be selected with respect to the application and only some stages (such as CDS only or CDS and amplification) may be parallelized. Alternatively or in addition, the parallelization may only regard a subset of the columns in the selected row.
In many applications, as the speed requirements increase, the number of readout channels needs to be increased as well. Each readout channel then advantageously includes CDS amplifier and ADC. Theoretically, the achievable frame rate of a CIS linearly increases with the number of readout elements working in parallel. In fact, the readout elements can be seen as a single readout channel with effective speed boosted by the number of replicas. In practice, this parallelism can be increased as much as needed. Nowadays many CIS implementations employ a readout element per pixel column, so that such readout element is in charge of processing the signal coming from pixels in a single column. Moreover, parallelism can be increased further by implementing more than one readout element per pixel column. In such a case, a number of readout elements processes a number of pixels within the same column. This means that a plurality of rows is read out simultaneously. This technique has been proven useful for very high-speed CIS, giving rise to thousands of frames per second for resolutions around 1 mega pixel (Mp).
However, for ultra-high speed CIS, the increasing of the parallelism may require a prohibitively large amount of readout channels. These readout channels may then suffer from an extremely high power dissipation and silicon area occupation for their on-chip implementing. In these cases, improving the speed of the individual readout channel is mandatory to keep area and power consumption reasonably bounded.